The present invention relates to repeating/extending a bus in a bus architecture.
FIG. 1 is used to aid in the understanding of the concept of a master device and a slave device in a bus system as well as related signals. In this instance, the Peripheral Component Interconnect (PCI) bus architecture is used as an example to describe the concept. Coupled to the PCI bus A0 are a plurality of devices 11, 12, 13 designated as device A, device B and device C. These devices 11, 12,13 may be Input/Output (I/O) Controller, Direct Memory Access (DMA) Controller, Memory Controller and so forth which are capable of obtaining ownership of the PCI bus. A device that is capable of obtaining ownership of the PCI bus is known as a master device.
Generally, only one master device can own the bus at a time. The reason is that if two or more master devices own the bus at a time, address, data as well as control signals of one device will interfere with the signals of the other device. The determination as to which device is to own the PCI bus A0 is performed by an arbiter device 14. The arbiter device 14 typically grants access and ownership of the PCI bus A0 to one master device 11, 12, 13 based on an arbitration scheme. The master devices 11, 12, 13 are connected to the arbiter device 14 by individual control signal lines which are the request signal lines REQ#1, REQ#2, REQ#3 and the grant signal lines GNT#1, GNT#2, GNT#3. Any master device 11, 12, 13 that wishes to control the PCI bus A0 sends a request signal to the arbiter device 14 through the respective request signal lines REQ#1, REQ#2, REQ#3. Arbitration is performed where two or more request signals are received by the arbiter device 14 within the same time period. In one example, the arbitration may be merely determining the priority of the master devices 11, 12, 13 making the request. Once the determination is made, the arbiter device 14 issues a grant signal to that master device with the highest priority. For example, if device A 11 is determined to have the highest priority, the arbiter device 14 issues a grant signal over the grant signal line GNT#1 to the device A 11. The granted device A 11 can now assert control over the PCI bus A0 to perform its bus cycle and is the master device of the cycle. The device that the master device seeks to control is known as a slave device.
In this example, the slave device may be the memory device 15. Once the master device A 11 gains control of the PCI bus A0, the master device A 11 makes attempt to communicate with the slave device 15 by generating a control signal. When the slave device 15 acknowledges the control signal and places itself in the control of the master device A 11, a master-slave relationship is established.
FIG. 2 illustrates a handshaking protocol that is exchanged between a master device and a slave device during a bus cycle. The signal lines C/BE#, FRAME# and IRDY# are asserted by the master device. The signals TRDY# and DEVSEL# are asserted by the slave device. The AD signal lines will be discussed later. Generally, the protocol exchange may occur as follows. During the initial bus cycle, the master device asserts the FRAME# signal line to announce that an address and a command exist on the AD and the C/BE# signal lines, respectively. All potential slave devices receive the signal from the FRAME# signal line and prepare to receive the address. The master device may then drive the AD and the C/BE# lines following the announcement. The slave devices decode the address and the slave device which has an address match announces its presence by asserting the DEVSEL# signal line. The C/BE# signal line indicates to the slave devices whether the bus cycle is a write cycle or a read cycle. If it is a write cycle, the master device drives the data to the slave device through the AD signal lines. If it is a read cycle, the slave device drives the data to the master device through the AD signal lines. The transmission of data occurs when both the master device and the slave device have asserted the IRDY# signal the TRDY# signal respectively.
In certain instances, it is desirable for the master devices and the slave devices coupled to the PCI bus to be able to communicate with the master devices and the slave devices connected to a bus external to the PCI bus. The characteristics of the external bus is similar to the PCI bus and thus mirroring the address, data and control signals is sufficient. However, in one known method, such bus-to-bus connection is performed by a PCI-to-PCI bridge. A bridge generally allows transactions to occur between a master or a slave device in a first bus and a master and a slave device in a second bus. However, a bridge generally assumes that an address translation takes place between the address memory space of the first bus and the address space of the second bus. Furthermore, the bridge assumes that data is translated to match the data size of the first bus to the second bus. Furthermore, the bridge assumes that the control signals are translated such that a protocol between the first bus and the second bus can be established. Accordingly, a bridge is generally a large and complex circuitry requiring many latency cycles to perform the various transactions described above. Where a bus mirroring is to be performed, such complexity should not be required.
In another instance, the PCI bus described above is not accessible to the external world. Where the behavior of the bus is desired to be known in real time such as the handshaking protocol occurring between the devices coupled to the bus, the behavior remains unknown because there is no access to the bus. In this instance, bus mirroring with an external bus is desirable because by observing the behavior of the external bus that mirrors the internal bus, the behavior of the internal bus can be determined.
A method and apparatus is described that is related to repeating (extending) transactions on a bus. A plurality of buffer pairs are configured to direct a plurality of signals between a first bus and a second bus in a bus cycle. A circuit is configured to monitor a control signal to determine a bus location of a master device and the circuit is further configured to enable one buffer in the buffer pairs to control a direction of the plurality of signals between the first bus and the second bus.
Other features and advantages of the present invention will be apparent from the accompanying drawings and detailed description to be followed.